65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
nc ( TMS57002PH )
nc
v dd
gnd
nc
nc 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
nc
nc
gnd
gnd
nc
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 pin
no. i
i
? ? i
o
o
o
o
i
i
? ? o
i/o
i/o
i/o
i/o
i/o
i/o i/o synpol
bcko
nc
nc
lrcko
so0
so1
cas
ras
clksel
clkin
gnd
gnd
we
ed0 ( lsb )
ed1
ed2
ed3
ed4
ed5 signal 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 pin
no. ? ? i/o
i/o
o
o
? o
? o
o
? ? o
o
? o
i
i
i i/o nc
nc
ed6
ed7 ( msb )
ea0 ( lsb )
ea1
nc
ea2
nc
ea3
ea4
gnd
v dd
ea5
ea6
nc
ea7
test0
test1
test2 signal 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 pin
no. o
o
? ? i
i
i
i
? i
i
? ? i
i
o
i
o
o
i i/o ea8
ea9 ( msb )
nc
nc
d0 ( lsb )
d1
d2
d3
nc
d4
d5
v dd
v dd
d6
d7 ( msb )
pc0
bio
ovfa
ovfm
rs signal 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 pin
no. ? ? o
i
i
i
i
o
i
i
? ? ? ? i
i
? i
i
i i/o nc
nc
empty
mute
cs
wr
pload
nc/dready *
cload
strb
nc
v dd
gnd
nc
bcki
lrcki
nc
si0
si1
sync signal 64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nc
nc
v dd
v dd
nc
nc
nc
nc
v dd
gnd
nc
nc * : TMS57002PH ; nc. TMS57002PH ( 1/3 )
il00d c-mos digital audio signal processor
?op view
78
79
75
2
76
5
80
11
10
1
60
66
65
67
69
64
57
55
54
51
50
48
47
46
45
70
38
39
40 si0
si1
bcki
bcko
lrcki
lrcko
sync
clkin
clksel
synpol
rs
wr
cs
pload
cload
mute
bio
d7
d6
d5
d4
d3
d2
d1
d0
strb
test0
test1
test2 6
7
56
63
42
41
37
35
34
31
30
28
26
25
8
9
14
15
16
17
18
19
20
23
24
58
59
68 so0
so1
pc0
empty
ea9
ea8
ea7
ea6
ea5
ea4
ea3
ea2
ea1
ea0
cas
ras
we
ed7
ed6
ed5
ed4
ed3
ed2
ed1
ed0
ovfa
ovfm
dready TMS57002PH ( 2/3 ) input
bcki
bcko
bio
clkin
clksel
cload
cs
d0 - 7
dready
lrcki
lrcko
mute
pload
rs
si0, 1
strb
sync
synpol
test0 - 2
wr
output
cas
ea0 - 9
empty
ovfa
ovfm
pc0
ras
so0, 1
we
input/output
ed0 - 7
; bit clock for serial input
; bit clock for serial output
; branch control
; master clock
; clkin frequency select ( l ; 512 fs h ; 256 fs )
; counting load
; chip enable for parallel port
; parallel port
; data ready signal to host controller
; right and left channel threshold clock
for serial input
; right and left channel threshold clock
for serial output
; mute
; program load
; reset ( l ; reset h ; normal operation )
; serial input data 0, 1
; data strobe for parallel port
; program sync signal
; sync signal effective edge select
( l ; down h ; up )
; for test
; right enable for parallel port
; col address strobe for outer external ram
; outer external ram address
; counting buffer empty
; alu overflow flag ( open drain output )
; mac overflow flag ( open drain output )
; program counter 0
; row address strobe for outer external ram
; serial output data 0, 1
; right enable for outer external ram
; outer external ram data
program
ram 256 w x 24-bit data ram
bank 0 256 w x 24-bit data ram
bank 1 32 w x 24-bit coefficient
ram 256 w x 32-bit parallel
port coefficient
buffer
16 w x 32-bit external
ram
interface t-reg sequence
control status
register repeat
counter alu 32-bit 32-bit serial
port a-bus-24-bit b-bus-32-bit c-bus-32-bit d-bus-24-bit 32-bit 24-bit mac 24 x 32 + 52
= 52-bit acc control d0 - 7
45 - 48, 50,
51, 54, 55 ras ( 9 ) , cas ( 8 ) , we ( 14 ) ea0 - 9
26, 28, 30, 31, 34,
35, 37, 41, 42 ed0 - 7
( 15 - 20, 23, 24 ) control si0, si1 ( 78, 79 ) so0, so1 ( 6, 7 ) TMS57002PH ( 3/3 )
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